The complexity of modern, software-intensive systems continues to increase due to the rising number of features and functionalities.
For complex, safety-critical, and software-intensive systems, safety is of paramount importance. To ensure safety, these systems and their requirements are analyzed using established methods like FMEA, FTA, or HAZOP.
However, engineers still perform the safety analysis manually to identify potential safety flaws, which is time-consuming and error-prone.
Formal verification is a way to automate the verification process by letting an automatic model checker prove whether a system fulfils a certain requirement, e.
g., a safety property. Understanding the output of a model checker is already tough and subject to several approaches such as Property Specification Patterns (PSP), Domain-Specific Languages, and counterexample explanation techniques.
The main motive of this thesis is to find possible fixes that satisfies the violated system specification. Thus, fixes can be an input to the user to understand and modify the violated system specification.
While writing your thesis with us, you are responsible for the following tasks :
Start : According to prior agreement
Duration : 6 months
Requirement for this thesis is the enrollment at university. Please attach a motivation letter, your CV, transcript of records, examination regulations and if indicated a valid work and residence Permit.
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Arut Prakash Kaleeswaran (Business Department)
Arne Nordmann (Business Department)