Typically requires at least 3+ years of hands-on experience in timing, STA, CAD / methodology, etc.
Proficiency in STA and methodologies for timing closure, signal integrity analysis, cross-talk, and OCV (AOCV, POCV) effects, etc.
Experience with transistor-level tools such as NanoTime, PathMill, HSPICE.
Familiar with digital custom circuit designs including dynamic circuit techniques and memories as well as SPICE models and netlists.
Programming in Perl, TCL, or similar language.
Good communicator who can accurately describe issues and follow them through to completion.
Work with design teams to understand and debug tool issues and constraintsBuild / maintain flows, scripts and methodologies for transistor-level analysisWork closely with design teams and CAD to drive timing, power, signal integrity, and functional verification closure effortsDeep analysis of timing paths to identify key issuesCreate documentation and help with guidelines / specs
Education & Experience
BS, MS preferred, degree in technical field