Design Verification Engineer
vor 4 Tg.

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet?

Do you like changing the game? We have an opportunity for a visionary and unusually talented Design Verification Engineer.

As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day.

Do your life’s best work here at Apple! This role is for a DV engineer who will enable bug-free first silicon for the mixed-signal designs.

The responsibilities include all phases of pre-silicon verification including but not limited to : construction of verification environments, coding of test scenarios and assertions and close collaboration with Analog and Digital Design engineers.

Key Qualifications

  • Deep knowledge of System Verilog test-bench language and UVM
  • Hands-on experience with constrained random verification environments
  • Hands-on experience with Assertion Based Verification
  • Basic design background in support of verification results analysis
  • Knowledge of Object Oriented Programming
  • Familiarity with system design using C (C++) or Verilog is a plus
  • ATE functional test pattern generation for logic testers is a plus
  • Graduates are welcome to apply
  • Description

    Construction of verification environment by using Verilog, System Verilog or UVM Designing test plan for verification Coding test scenarios, assertion and debugging for Digital Design.

    Education & Experience

    Master Degree in Electrical Engineering or equivalent

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